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TSB41BA3B 数据表(PDF) 9 Page - Texas Instruments

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部件名 TSB41BA3B
功能描述  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
Download  67 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TSB41BA3B 数据表(HTML) 9 Page - Texas Instruments

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TSB41BA3B
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SLLS678 − SEPTEMBER 2005
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
TYPE
PFP
NO.
GGM
NO.
I/O
DESCRIPTION
AGND
Supply
21, 40, 43,
50, 61, 62
J9, A10,
B8, D6,
C2, C3
Analog circuit ground terminals. These terminals must be tied together to the
low-impedance circuit board ground plane.
AVDD
Supply
24, 39, 44,
51, 57, 63
H10, C9,
C8, E6,
B3, C1
Analog circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1
µF and 0.001 µF.
Lower frequency 10-
µF filtering capacitors are also recommended. These supply
terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE,
and DVDD-3.3 terminals internal to the device to provide noise isolation. The
PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc
impedance connection on the circuit board.
BMODE
CMOS
74
G1
I
Beta-mode input. This terminal determines the PHY-link interface connection
protocol. When logic-high (asserted), the PHY-link interface complies with the
1394b-2002 B PHY-link interface. When logic-low (deasserted), the PHY-link
interface complies with the legacy 1394a-2000 standard. When using an LLC such
as the 1394b-2002 TSB82AA2, this terminal must be pulled high. When using an
LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low.
NOTE: The PHY-link interface cannot be changed between the different protocols
during operation.
CPS
CMOS
34
E8
I
Cable-power status input. This terminal is normally connected to cable power
through a 400-k
Ω resistor. This circuit drives an internal comparator that detects the
presence of cable power. This transition from cable power sensed to cable power
not sensed can be used to generate an interrupt to the LLC.
CTL0
CTL1
CMOS
9
10
K5
J5
I/O
Control I/Os. These bidirectional signals control communication between the
TSB41BA3B and the LLC. Bus holders are built into these terminals.
D0−D7
CMOS
11, 12, 13,
15, 16, 17,
19, 20
K6, J6,
H6, K7,
J7, K8, K9,
K10
I/O
Data I/Os. These are bidirectional data signals between the TSB82BA3 and the
LLC. Bus holders are built into these terminals.
If power management control (PMC) is selected using LCLK_PMC, then some of
these terminals can be used for PMC. See the LCLK_PMC terminal description for
more information.
DGND
Supply
4, 14, 38,
64, 72, 76
H3, G7,
C10, D2,
F1, G3
Digital circuit ground terminals. These terminals must be tied together to the
low-impedance circuit board ground plane.
DVDD-CORE
Supply
8, 37, 65,
71
H4, D8,
D1, E5
Digital core circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1
µF and 0.001 µF.
An additional 1-
µF capacitor is required for voltage regulation. These supply
terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and
AVDD terminals internal to the device to provide noise isolation.
DVDD-3.3
Supply
6, 18, 69,
70
J4, J8, E3,
E4
Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1
µF and 0.001 µF.
Lower-frequency 10-
µF filtering capacitors are also recommended. The DVDD-3.3
terminals must be tied together at a low-impedance point on the circuit board. These
supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3,
DVDD-CORE, and AVDD terminals internal to the device to provide noise isolation.
The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low
dc impedance connection on the circuit board.


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