DSPA56720AG datasheet(36/54 Pages) FREESCALE

部件名	DSPA56720AG

功能描述	SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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36 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

36

320

Write data strobe assertion width

7

HACK write assertion width

–

13.2

–

ns

321

Write data strobe deassertion width

7

HACK write deassertion width

• after ICR, CVR and “Last Data Register” writes

4

2

× T

C + 6.6

16.6

–

ns

• after IVR writes, or

• after TXH:TXM writes (with HBE=0), or

• after TXL:TXM writes (with HBE=1)

–16.5

–

322

HAS assertion width

–

9.9

–

ns

323

HAS deassertion to data strobe assertion

8

–0.0

–

ns

324

Host data input setup time before write data strobe deassertion

7

Host data input setup time before HACK write deassertion

–9.9

–

ns

325

Host data input hold time after write data strobe deassertion

7

Host data input hold time after HACK write deassertion

–3.3

–

ns

326

Read data strobe assertion to output data active from high impedance

3

HACK read assertion to output data active from high impedance

–3.3

–

ns

327

Read data strobe assertion to output data valid

3

HACK read assertion to output data valid

––

24.2

ns

328

Read data strobe deassertion to output data high impedance

3

HACK read deassertion to output data high impedance

––

9.9

ns

329

Output data hold time after read data strobe deassertion

3

Output data hold time after HACK read deassertion

–3.3

–

ns

330

HCS assertion to read data strobe deassertion

3

TC + 9.9

14.9

–

ns

331

HCS assertion to write data strobe deassertion

7

–9.9

–

ns

332

HCS assertion to output data valid

–

19.1

ns

333

HCS hold time after data strobe deassertion

8

–0.0

–

ns

334

Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)

–

4.7

–

ns

335

Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)

–

3.3

–

ns

336

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data

strobe assertion

8

•Read

–0

–

ns

• Write

–4.7

–

337

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe

deassertion

8

–3.3

–

ns

338

Delay from read data strobe deassertion to

host request assertion for “Last Data Register” read

3, 4, 9

TC

5.0

–

ns

Table 18. HDI24 Timing Parameters (Continued)

No.

Characteristics

2

Expression

200 MHz

Unit

Min

Max

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