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TC74ACT163P 数据表(PDF) 6 Page - Toshiba Semiconductor |
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TC74ACT163P 数据表(HTML) 6 Page - Toshiba Semiconductor |
6 / 13 page TC74ACT161,163P/F/FN 2007-10-01 6 Electrical Characteristics DC Characteristics Test Condition Ta = 25°C Ta = −40 to 85°C Characteristics Symbol VCC (V) Min Typ. Max Min Max Unit High-level input voltage VIH ⎯ 4.5 to 5.5 2.0 ⎯ ⎯ 2.0 ⎯ V Low-level input voltage VIL ⎯ 4.5 to 5.5 ⎯ ⎯ 0.8 ⎯ 0.8 V High-level output voltage VOH VIN = VIH or VIL IOH = −50 μA IOH = −24 mA IOH = −75 mA (Note) 4.5 4.5 5.5 4.4 3.94 ⎯ 4.5 ⎯ ⎯ ⎯ ⎯ ⎯ 4.4 3.80 3.85 ⎯ ⎯ ⎯ V Low-level output voltage VOL VIN = VIH or VIL IOL = 50 μA IOL = 24 mA IOL = 75 mA (Note) 4.5 4.5 5.5 ⎯ ⎯ ⎯ 0.0 ⎯ ⎯ 0.1 0.36 ⎯ ⎯ ⎯ ⎯ 0.1 0.44 1.65 V Input leakage current IIN VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA ICC VIN = VCC or GND 5.5 ⎯ ⎯ 8.0 ⎯ 80.0 μA Quiescent supply current IC Per input: VIN = 3.4 V Other input: VCC or GND 5.5 ⎯ ⎯ 1.35 ⎯ 1.5 mA Note: This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. Timing Requirements (input: tr = tf = 3 ns) Test Condition Ta = 25°C Ta = −40 to 85°C Characteristics Symbol VCC (V) Limit Limit Unit Minimum pulse width (CK) tW (L) tW (H) Figure 1 5.0 ± 0.5 5.0 5.0 ns Minimum pulse width ( CLR ) (Note1) tW (L) Figure 4 5.0 ± 0.5 5.0 5.0 ns Minimum pulse width ( LOAD , ENP, ENT) ts Figure 2, Figure 3 5.0 ± 0.5 6.0 6.0 ns Minimum set-up time (A, B, C, D) ts Figure 2 5.0 ± 0.5 4.0 4.0 ns Minimum set-up time ( CLR ) (Note 2) ts Figure 5 5.0 ± 0.5 3.0 3.0 ns Minimum hold time ( LOAD , ENP, ENT) th Figure 2, Figure 3 5.0 ± 0.5 1.0 1.0 ns Minimum hold time (A, B, C, D) th Figure 2 5.0 ± 0.5 2.0 2.0 ns Minimum hold time ( CLR ) (Note 2) th Figure 5 5.0 ± 0.5 2.0 2.0 ns Minimum removal time ( CLR ) (Note 1) trem Figure 4 5.0 ± 0.5 1.0 1.0 ns Note 1: For TC74ACT161 only Note 2: For TC74ACT163 only |
类似零件编号 - TC74ACT163P |
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类似说明 - TC74ACT163P |
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