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OUTPUT RANGE

V

V

-

REFH

REFL

65536

´ CODE

BufferGain+V

´

REFL

V

OUT

=

(1)

INPUT DATA FORMAT

POWER DOWN

HARDWARE RESET

DAC8881

SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007

GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is

output saturation occurs. The DAC8881 output transfer function is given in Equation 1:

Where:

CODE = 0 to 65535. This is the digital code loaded to the DAC.

Buffer Gain = 1 or 2 (set by the GAIN pin).

straight binary, as shown in Table 1. When this pin is connected to DGND, the input data format is two's

complement, as shown in Table 2.

Table 1. Output vs Straight Binary Code

USB CODE

5V RANGE

DESCRIPTION

FFFFh

+4.99992

+Full-Scale – 1LSB

C000h

+3.75000

3/4-Scale

8000h

+2.50000

Midscale

4000h

+1.25000

1/4-Scale

0000h

0.00000

Zero-Scale

Table 2. Output vs Two's Complement Code

BTC CODE

5V RANGE

DESCRIPTION

7FFFh

+4.99992

+Full-Scale – 1LSB

4000h

+3.75000

3/4-Scale

0000h

+2.50000

Midscale

FFFFh

+2.49992

Midscale – 1LSB

C000h

+1.25000

1/4-Scale

8000h

0.00000

Zero-Scale

The DAC8881 has a hardware power-down function. When the PDN pin is high, the device is in power-down

register and the DAC latch do not change. In power-down mode, SPI communication is still active.

When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to

the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode.

26

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Product Folder Link(s): DAC8881