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74LVC2G74DP 数据表(PDF) 11 Page - NXP Semiconductors |
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74LVC2G74DP 数据表(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 11 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time mnb142 trec tPHL tPHL tW tPLH tPLH VM VM VM tW VM VM VI GND VI GND SD input VI GND RD input CP input VOH VOL Q output VOH VOL Q output trec |
类似零件编号 - 74LVC2G74DP |
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类似说明 - 74LVC2G74DP |
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