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74LVC1G80GW 数据表(PDF) 8 Page - NXP Semiconductors

部件名 74LVC1G80GW
功能描述  Single D-type flip-flop; positive-edge trigger
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

74LVC1G80GW 数据表(HTML) 8 Page - NXP Semiconductors

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74LVC1G80_8
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 08 — 29 August 2007
8 of 16
NXP Semiconductors
74LVC1G80
Single D-type flip-flop; positive-edge trigger
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 7.
Clock (CP) to output (Q) propagation delay times
mna652
CP input
Q output
tPLH
tPHL
VM
VM
VOH
VI
GND
D input
VI
GND
VOL
VM
VM
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8.
Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold
times and maximum clock pulse frequency
mna653
th
tsu(L)
th
tPLH
tW
tPHL
tsu(H)
1/fmax
VM
VM
VM
VI
GND
VI
GND
CP input
D input
VOH
VOL
Q output


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