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74AVCH1T45GM 数据表(PDF) 2 Page - NXP Semiconductors |
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74AVCH1T45GM 数据表(HTML) 2 Page - NXP Semiconductors |
2 / 22 page 74AVCH1T45_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 25 October 2007 2 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state x 240 Mbit/s (translate to 1.2 V) s Suspend mode s Bus hold on data inputs s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °Cto+85 °C and −40 °C to +125 °C 3. Ordering information 4. Marking 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH1T45GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AVCH1T45GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 Table 2. Marking Type number Marking code 74AVCH1T45GW K5 74AVCH1T45GM K5 Fig 1. Logic symbol Fig 2. Logic diagram 001aag885 VCC(B) VCC(A) 5 DIR 3 A B 4 001aag886 VCC(B) VCC(A) DIR A B |
类似零件编号 - 74AVCH1T45GM |
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类似说明 - 74AVCH1T45GM |
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