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RT8801 数据表(PDF) 5 Page - Richtek Technology Corporation |
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RT8801 数据表(HTML) 5 Page - Richtek Technology Corporation |
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5 / 23 page  RT8801 Preliminary 5 DS8801-04 August 2007 www.richtek.com All brandname or trademark belong to their owner respectively Functional Pin Description SLOT_OCC (Pin 1) CPU socket occupied; the signal is defined to indicate if the CPU has been changed/ removed and it will reset all chip. There is one register implemented for the status indication. The register will be reset when the VDD power removed or CPU changed/removed. The pin is implemented as an input, TTL level, and active-low signal. DATA (Pin 2), CLK (Pin 3) 2-wires programming interface. RST (Pin 4) This pin be pull low (the Watching Dog = Low), it will reset some register, when 0x03 bit 0 be setting. AD_SEL (Pin 5) The pin select series bus address. Pin =1,Address = 0x5E & Pin = 0, Address = 0x5C. GND (Pin 6, Bottom Pad) Chip power ground. IC_OUT (Pin 7) The pin is defined as a reference current output. A capacitor is attached to set the default Watching Dog low pluse time. Write the index 0x03 bit0 = 1 delay 7 times Tdelay time then issue Tdelay low pluse. FB (Pin 8) The pin is defined as an inverting input of internal error amplifier. COMP (Pin 9) The pin is defined as an output of the error amplifier and an input of the PWM comparator. SGND (Pin 10) Difference ground sense of VCORE. VOSS (Pin 11) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. C_OUT C_OUT OUT delay x V I C T where = DVD (Pin 12) Hardware adjustable system power UVLO detection; input pin; the internal trip threshold = 0.9V at VDVD rising. SS (Pin 13) The pin is defined to set soft-start ramp rate; a capacitor is attached to set the start time interval. Pull this pin lower than 1.0V (ramp valley of saw-tooth wave in pulse width modulator) will shut the converter down. PGOOD (Pin 14) Power Good Indication. PGOOD is an open drain output. PGOOD will go high impedance when SS voltage greater than 3.7V and no fault occurs. RT (Pin 15) Default operation switching frequency setting. A resistor is attached to set the default operation frequency. CSN (Pin 16) The pin is defined to sense load current of CPU. The pin should be connected to the output node of choke. ADJ (Pin 17) Pin for active droop adjustment. An external resistor is attached to GND for load droop setting. CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19), CSP4 (Pin 18) Current sense inputs from the individual converter channels. PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24), PWM4 (Pin 25) PWM outputs for each phase switching drive. VDD (Pin 26) Chip powers supply. Connect this pin to a 5VSB or VCC5 supply. |
类似零件编号 - RT8801 |
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类似说明 - RT8801 |
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