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74VHC595MTC 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74VHC595MTC 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 12 page ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC595 Rev. 1.2 2 Connection Diagram Pin Description Logic Symbol IEEE/IEC Truth Table Pin Names Description SER Serial Data Input SCK Shift Register Clock Input (Active rising edge) RCK Storage Register Clock Input (Active rising edge) SCLR Reset Input G 3-STATE Output Enable Input (Active LOW) QA – QH Parallel Data Outputs Q’H Serial Data Output Inputs Function SER RCK SCK SCLR G XXXX H QA thru QH 3-STATE XXXX L QA thru QH outputs enabled XXX LL Shift Register cleared: Q ′ H = 0 LX ↑ HL Shift Register clocked: QN = Qn-1, Q0 = SER = L HX ↑ HL Shift Register clocked: QN = Qn-1, Q0 = SER = H X ↑ XH L Contents of Shift Register transferred to output latches |
类似零件编号 - 74VHC595MTC |
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类似说明 - 74VHC595MTC |
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