2002 Nov 12

2

Philips Semiconductors

Preliminary specification

Inverter

74AUC1G04

FEATURES

• Wide supply voltage range from 0.8 to 2.7 V

• High noise immunity

• Complies with JEDEC standard:

– JESD76 (1.65 to 1.95 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• ESD protection:

2000 V Human Body Model (A 114-A)

200 V Machine Model (A 115-A)

• 3.3 V tolerant inputs/outputs

• SC-88A and SC-74A package.

DESCRIPTION

The 74AUC1G04 is a high-performance, low-power,

low-voltage, Si-gate CMOS device.

Schmitt-trigger action at all inputs makes the circuit

tolerant for slower input rise and fall time.

This device is fully specified for partial power-down

preventing the damaging current backflow through the

device when it is powered down.

The 74AUC1G04 provides the inverting buffer.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay input A to output Y

4.4

ns

1.8

ns

1.3

ns

1.4

ns

1.2

ns

input capacitance

4

pF

power dissipation capacitance per buffer

14

pF