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MCM20014IBMN 数据表(PDF) 48 Page - Motorola, Inc |
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MCM20014IBMN 数据表(HTML) 48 Page - Motorola, Inc |
48 / 54 page MOTOROLA MCM20014 48 Figure 27. I2C Bus Timing Diagram I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS (see Figure 27) Symbol Characteristic Min Max Unit fmax SCLK maximum frequency 50 400 KHz M1 Start condition SCLK hold time 4 - TMCLK 7 M2 SCLK low period 8 - TMCLK M3 SCLK/SDATA rise time [from VIL = (0.2)*VDD to VIH = (.8)*VDD] -.3 µs8 M4 SDATA hold time 4 - TMCLK 7 M5 SCLK/SDATA fall time (from Vh = 2.4V to Vl = 0.5V) - .3 µs8 M6 SCLK high period 4 - TMCLK M7 SDATA setup time 4 - TMCLK 7 M8 Start / Repeated Start condition SCLK setup time 4 - TMCLK M9 Stop condition SCLK setup time 4 - TMCLK CI Capacitive for each I/O pin - 10 pF Cbus Capacitive bus load for SCLK and SDATA - 200 pF Rp Pull-up Resistor on SCLK and SDATA 1.5 10 k Ω9 6 I2C is a proprietary Philips interface bus 7 The unit T MCLK is the period of the input master clock; The frequency of MCLK is assumed 13.5 MHz 8 The capacitive load is 200 pF 9 A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200 pf, the minimum value of Rp should be selected in order to meet specifications M1 SCLK M3 M5 VIH VIL M2 M6 SDATA M4 M7 M8 M9 M8 |
类似零件编号 - MCM20014IBMN |
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类似说明 - MCM20014IBMN |
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