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AT847S25 数据表(PDF) 1 Page - Power Semiconductors

部件名 AT847S25
功能描述  PHASE CONTROL THYRISTOR
Download  4 Pages
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制造商  POSEICO [Power Semiconductors]
网页  http://www.poseico.com
标志 POSEICO - Power Semiconductors

AT847S25 数据表(HTML) 1 Page - Power Semiconductors

  AT847S25 Datasheet HTML 1Page - Power Semiconductors AT847S25 Datasheet HTML 2Page - Power Semiconductors AT847S25 Datasheet HTML 3Page - Power Semiconductors AT847S25 Datasheet HTML 4Page - Power Semiconductors  
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PHASE CONTROL THYRISTOR
AT847
Repetitive voltage up to
2500 V
Mean on-state current
2980 A
Surge current
39.2 kA
FINAL SPECIFICATION
feb 97 - ISSUE : 02
Symbol
Characteristic
Conditions
Tj
[°C]
Value
Unit
BLOCKING
V RRM
Repetitive peak reverse voltage
125
2500
V
V RSM
Non-repetitive peak reverse voltage
125
2600
V
V DRM
Repetitive peak off-state voltage
125
2500
V
I RRM
Repetitive peak reverse current
V=VRRM
125
200
mA
I DRM
Repetitive peak off-state current
V=VDRM
125
200
mA
CONDUCTING
I T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
2980
A
I T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
2370
A
I TSM
Surge on-state current
sine wave, 10 ms
125
39.2
kA
I² t
I² t
without reverse voltage
7683 x1E3
A²s
V T
On-state voltage
On-state current =
2100 A
25
1.22
V
V T(TO)
Threshold voltage
125
0.85
V
r T
On-state slope resistance
125
0.175
mohm
SWITCHING
di/dt
Critical rate of rise of on-state current, min.
From 75% VDRM up to 3280 A, gate 10V 5ohm
125
800
A/µs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 70% of VDRM
125
1000
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 10V, 10 ohm , tr=.5 µs
25
2
µs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/µs linear up to 75% VDRM
400
µs
Q rr
Reverse recovery charge
di/dt=-20 A/µs, I= 2150 A
125
µC
I rr
Peak reverse recovery current
VR= 50 V
A
I H
Holding current, typical
VD=5V, gate open circuit
25
500
mA
I L
Latching current, typical
VD=12V, tp=30µs
25
1000
mA
GATE
V GT
Gate trigger voltage
VD=12V
25
3.5
V
I GT
Gate trigger current
VD=12V
25
400
mA
V GD
Non-trigger gate voltage, min.
VD=VDRM
125
0.25
V
V FGM
Peak gate voltage (forward)
30
V
I FGM
Peak gate current
10
A
V RGM
Peak gate voltage (reverse)
10
V
P GM
Peak gate power dissipation
Pulse width 100 µs
150
W
P G
Average gate power dissipation
10
W
MOUNTING
R th(j-h)
Thermal impedance, DC
Junction to heatsink, double side cooled
11
°C/kW
R th(c-h)
Thermal impedance
Case to heatsink, double side cooled
2
°C/kW
T j
Operating junction temperature
-30 / 125
°C
F
Mounting force
40.0 / 50.0
kN
Mass
1700
g
ORDERING INFORMATION : AT847 S 25
standard specification
VDRM&VRRM/100
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
ANSALDO
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori


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