HV301_05 Datasheet(数据表) 5 Page

5 page

HV301/HV311

A092605

RAMP pin current is reduced to zero and the voltage on the

RAMP pin will be fixed, indicating that the circuit is in current limit

mode. Depending on the value of the load capacitor and the

programmed current limit, charging may continue for some time,

but may not exceed a nominal 100ms preset time limit. Once the

load capacitor has been charged, the output current will drop,

reducing the voltage on the SENSE pin, which in turn will

increase the RAMP pin current, thus causing the voltage on the

capacitor connected to the RAMP pin to continue rising, thereby

providing yet another programmed delay. If due to output over-

load conditions during startup, PWRGD does not achieve an

active state within 100ms or the Circuit Breaker is tripped, the

circuit is reset, pulling down the GATE to V

EE, discharging the

capacitor connected to the RAMP pin, changing PWRGD to an

inactive state. A timeout or circuit breaker fault will initiate an

Auto-Retry if enabled.

On the other hand, in feedback capacitor mode, a current source

of 10µA from the RAMP pin limits the dv/dt of the feedback

capacitor which, in turn, programs Inrush according to

Inrush=10µA-C

load/C2.

When the ramp voltage is within 1.2V of the regulated internal

supply voltage, the controller will force the GATE terminal to a

nominal 10V, the PWRGD pin will change to an active state, the

Circuit Breaker is enabled and the circuit will transition to a low

power sleep mode.

When the voltage on the SENSE pin rises to 100mV, indicating

an over current condition, the circuit breaker will trip in less than

5µs. This time may be extended by the addition of external

components.

At any time during the start up cycle or thereafter, crossing the

UV and OV limits (including hysteresis) will cause an immediate

reset of all internal circuitry. When the input supply voltage

returns to a value within the programmed UV and OV limits a new

start up sequence will be initiated.

Functional Description, cont’d.

Design Information

Setting Under Voltage and Over Voltage Shut Down

The UV and OV pins are connected to comparators with nominal

1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV).

They are used to detect under voltage and over voltage condi-

tions at the input to the circuit. Whenever the OV pin rises above

its high threshold (1.26V) or the UV pin falls below its low

threshold (1.16V) the GATE voltage is immediately pulled low,

the PWRGD pin changes to its inactive state and the external

capacitor connected to the RAMP pin is discharged.

Calculations can be based on either the desired input voltage

operating limits or the input voltage shutdown limits. In the

following equations the shutdown limits are assumed.

The under voltage and over voltage shut down thresholds can be

programmed by means of the three resistor divider formed by

R1, R2 and R3. Since the input currents on the UV and OV pins

are negligible the resistor values may be calculated as follows:

OFF

UVL

EEUV off

OFF

OVH

EEOV off

116

126

()

Where |

EEUV(off)| and |VEEOV(off)| relative to VEE are Under & Over

Voltage Shut Down Threshold points.

If we select a divider current of 100µA at a nominal operating

input voltage of 50 Volts then

100

500

Ω

From the second equation for an OV shut down threshold of 65V

the value of R3 may be calculated.

OFF ==

126

500

1 26 500

969

Ω

The closest 1% value is 9.76k

Ω.

From the first equation for a UV shut down threshold of 35V the

value of R2 can be calculated.

OFF ==

×+

(

)

−=

116

500

1 16

500

976

6 81

Ω

ΩΩ

The closest 1% value is 6.81k

Ω.

Then

500

483

−−=

ΩΩ

The closest 1% value is 487k

Ω.

HV301_05 Datasheet(数据表) 5 Page - Supertex, Inc

HV301 Datasheet(HTML) 5 Page - Supertex, Inc

HTML 页

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

相关电子零件

链接网址