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CAT24WC03J-1.8TE13 数据表(PDF) 4 Page - Catalyst Semiconductor |
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CAT24WC03J-1.8TE13 数据表(HTML) 4 Page - Catalyst Semiconductor |
4 / 14 page Discontinued Parts CAT24WC03/05 4 Doc. No. 1005, Rev. F © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT24WC03/05 supports the I2C Bus data trans- mission protocol. This Inter-Integrated Circuit Bus proto- col defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC03/05 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices (24WC03) and 4 devices (24WC05) may be connected to the bus as determined by the device address inputs A0, A1, and A2. PIN DESCRIPTIONS SCL: Serial Clock The CAT24WC03/05 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24WC03/05 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading mul- tiple devices. When these pins are left floating the default values are zeros. A maximum of eight devices can be cascaded when using the CAT24WC03. All three address pins are used for CAT24WC03. If only one CAT24WC03 is addressed on the bus, all three address pins (A0, A1, and A2) can be left floating or connected to VSS. Figure 2. Write Cycle Timing Figure 1. Bus Timing Figure 3. Start/Stop Timing |
类似零件编号 - CAT24WC03J-1.8TE13 |
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类似说明 - CAT24WC03J-1.8TE13 |
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