数据搜索系统,热门电子元器件搜索 |
|
FM24C256 数据表(PDF) 7 Page - Ramtron International Corporation |
|
FM24C256 数据表(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C256 Rev 3.1 May 2005 Page 7 of 12 S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A Figure 9. Selective (Random) Read Endurance A FRAM internally operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read and write access. The FRAM architecture is based on an array of rows and columns. Rows (A14-A6) are subdivided into 8 segments (A5-A3). Each access causes an endurance cycle for a row segment. In the FM24C256, there are 8 bytes per segment. Endurance can be optimized by ensuring frequently accessed data is located in different segments. Regardless, FRAM read and write endurance is effectively unlimited at the 1MHz two-wire speed. Even at 30 accesses per second to the same segment, 10 years time will elapse before 10 billion endurance cycles occur. |
类似零件编号 - FM24C256_05 |
|
类似说明 - FM24C256_05 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |