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TSL201R-LF 数据表(PDF) 2 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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TSL201R-LF 数据表(HTML) 2 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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2 / 10 page  TSL201R−LF 64 y 1 LINEAR SENSOR ARRAY TAOS077B − MAY 2007 2 r r Copyright E 2007, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION AO 3 Analog output. CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 6, 7 Ground (substrate). All voltages are referenced to the substrate. SI 1 Serial input. SI defines the start of the data-out sequence. VDD 4 Supply voltage. Supply voltage for both analog and digital circuits. Detailed Description The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 66th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee) (tint) where: Vout is the analog output voltage for white condition Vdrk is the analog output voltage for dark condition Re is the device responsivity for a given wavelength of light given in V/(μJ/cm2) Ee is the incident irradiance in μW/cm2 tint is integration time in seconds AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. † For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. |
类似零件编号 - TSL201R-LF |
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类似说明 - TSL201R-LF |
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