SC16C2550BIB48 datasheet(7/43 Pages) PHILIPS

部件名	SC16C2550BIB48

功能描述	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

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制造商	PHILIPS [NXP Semiconductors]

网页	http://www.nxp.com

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7 / 43 page

SC16C2550B_4

Product data sheet

Rev. 04 — 15 February 2007

7 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

RESET

24

35

39

36

I

Reset (active HIGH). A logic 1 on this pin will reset the internal

registers and all the outputs. The UART transmitter output and

the receiver input will be disabled during reset time. (See

Section 7.10 “SC16C2550B external reset condition” for

initialization details.)

RXRDYA-

-

34

31

O

Receive Ready A, B (active LOW). This function is associated

with PLCC44 and LQFP48 packages only. This function

provides the RX FIFO/RHR status for individual receive

channels (A-B). RXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the receive data FIFOs. A logic 0

indicates there is a receive data to read/upload, that is, receive

ready status with one or more RX characters available in the

FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty

or when the programmed trigger level has not been reached.

This signal can also be used for single mode transfers (DMA

mode 0).

RXRDYB -

-

23

18

O

TXRDYA

-

1

43

O

Transmit Ready A, B (active LOW). This function is

associated with PLCC44 and LQFP48 packages only. These

outputs provide the TX FIFO/THR status for individual transmit

channels (A, B). TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An

individual channel’s TXRDYA, TXRDYB buffer ready status is

indicated by logic 0, that is, at least one location is empty and

available in the FIFO or THR. This pin goes to a logic 1 (DMA

mode 1) when there are no more empty locations in the FIFO

or THR. This signal can also be used for single mode transfers

(DMA mode 0).

TXRDYB

-

12

6

O

VCC

26

40

44

42

I

Power supply input.

XTAL1

10

16

18

13

I

Crystal or external clock input. Functions as a crystal input

or as an external clock input. A crystal can be connected

between this pin and XTAL2 to form an internal oscillator

circuit. Alternatively, an external clock can be connected to this

pin to provide custom data rates. (See Section 6.5

“Programmable baud rate generator”.) See Figure 6.

XTAL2

11

17

19

14

O

Output of the crystal oscillator or buffered clock. (See also

XTAL1.) Crystal oscillator output or buffered clock output.

Should be left open if an external clock is connected to XTAL1.

For extended frequency operation, this pin should be tied to

VCC via a 2 kΩ resistor.

CDA

-

38

42

40

I

Carrier Detect (active LOW). These inputs are associated

with individual UART channels A through B. A logic 0 on this

pin indicates that a carrier has been detected by the modem for

that channel.

CDB

-

19

21

16

I

CTSA

25

36

40

38

I

Clear to Send (active LOW). These inputs are associated with

individual UART channels, A through B. A logic 0 on the CTS

pin indicates the modem or data set is ready to accept transmit

data from the SC16C2550B. Status can be tested by reading

MSR[4]. This pin has no effect on the UART’s transmit or

receive operation.

CTSB

16

25

28

23

I

Table 3.

Pin description …continued

Symbol

Type

Description

HVQFN32 DIP40 PLCC44 LQFP48

类似零件编号 - SC16C2550BIB48

制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C2550BIB48	200Kb / 42P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 02-14 December 2004
NXP Semiconductors	SC16C2550BIB48	221Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 05-12 January 2009

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类似说明 - SC16C2550BIB48

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