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S-1122B40MC-L8ZTFG 数据表(PDF) 16 Page - Seiko Instruments Inc |
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S-1122B40MC-L8ZTFG 数据表(HTML) 16 Page - Seiko Instruments Inc |
16 / 29 page HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR S-1112/1122 Series Rev.5.0_00 16 Seiko Instruments Inc. Precautions • Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low. When mounting an output capacitor between the VOUT and VSS pins (CL) and a capacitor for stabilizing the input between VIN and VSS pins (CIN), the distance from the capacitors to these pins should be as short as possible. • Note that the output voltage may increase when a series regulator is used at low load current (1.0 mA or less). • Generally a series regulator may cause oscillation, depending on the selection of external parts. The following conditions are recommended for this IC. However, be sure to perform sufficient evaluation under the actual usage conditions for selection, including evaluation of temperature characteristics. Input capacitor (CIN): 1.0 µF or more Output capacitor (CL): 0.47 µF or more Equivalent series resistance (ESR): 10 Ω or less • The voltage regulator may oscillate when the impedance of the power supply is high and the input capacitor is small or an input capacitor is not connected. • The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • In determining the output current, attention should be paid to the output current value specified in Table 7 in the electrical characteristics and footnote *5 of the table. • SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. |
类似零件编号 - S-1122B40MC-L8ZTFG |
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类似说明 - S-1122B40MC-L8ZTFG |
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