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S-1122B18MC-L8DTFG Datasheet(数据表) 14 Page - Seiko Instruments Inc

部件型号  S-1122B18MC-L8DTFG
说明  HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
下载  29 Pages
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制造商  SII [Seiko Instruments Inc]
网页  http://www.sii.co.jp
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 14 page
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HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1112/1122 Series
Rev.5.0_00
14
Seiko Instruments Inc.
Operation
1. Basic operation
Figure 12 shows the block diagram of the S-1112/1122 Series.
The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-
divided by feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
Reference voltage
circuit
VOUT
*1
*1. Parasitic diode
VSS
VIN
Rs
Rf
Error
amplifier
Current
supply
Vref
+
Vfb
Figure 12
2. Output transistor
The S-1112/1122 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that VOUT does not exceed VIN
+ 0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from VOUT pin through a parasitic diode to VIN pin.




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