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SI5325B-B-GM 数据表(PDF) 3 Page - Silicon Laboratories |
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SI5325B-B-GM 数据表(HTML) 3 Page - Silicon Laboratories |
3 / 14 page Si5325 Preliminary Rev. 0.26 3 Rise/Fall Time CKOTRF 20–80% — 230 350 ps Duty Cycle CKODC 45 — 55 % PLL Performance Jitter Generation JGEN fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz — 0.6 TBD ps rms 12 kHz–20 MHz — 0.6 TBD ps rms 800 Hz–80 MHz — TBD TBD ps rms Jitter Transfer JPK —0.05 0.1 dB Phase Noise CKOPN fOUT = 622.08 MHz 100 Hz offset — TBD TBD dBc/Hz 1 kHz offset — TBD TBD dBc/Hz 10 kHz offset — TBD TBD dBc/Hz 100 kHz offset — TBD TBD dBc/Hz 1 MHz offset — TBD TBD dBc/Hz Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Off- set — TBD TBD dBc Spurious Noise SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) — TBD TBD dBc Package Thermal Resistance Junction to Ambient θJA Still Air — 38 — ºC/W Table 2. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.6 V LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V Operating Junction Temperature TJCT –55 to 150 C Storage Temperature Range TSTG –55 to 150 C ESD HBM Tolerance (100 pF, 1.5 k Ω)2 kV ESD MM Tolerance 200 V Latch-Up Tolerance JESD78 Compliant Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. |
类似零件编号 - SI5325B-B-GM |
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类似说明 - SI5325B-B-GM |
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