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SI8502-B-GM 数据表(PDF) 4 Page - Silicon Laboratories |
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SI8502-B-GM 数据表(HTML) 4 Page - Silicon Laboratories |
4 / 24 page Si85xx 4 Preliminary Rev. 0.1 1. Electrical Specifications Table 1. Electrical Specifications TA = –40 to +85 ºC (typical specified at 25 ºC), VDD = 2.7 to 5.5 V Parameter Conditions Min Typ Max Unit Supply Voltage (VDD) 2.7 — 5.5 V Supply Current Fully enabled, input frequency = 1MHz — 4 7 mA Undervoltage Lockout (VUVLO) 2.1 2.3 2.5 V Undervoltage Lockout Hysteresis (VHYST) — 100 — mV Logic Input HIGH Level MODE, R1, R2, R3, R4 inputs (TTL compatible) 2.0 — — V Logic Input LOW Level — — 0.8 V Reset Time (tR) 250 — — ns R1, R2, R3, R4 Input Rise Time (tRR) — — 30 ns R1, R2, R3, R4 Input Fall Time (tFR) — — 30 ns Measurement Watchdog Timeout (tWD) 30 50 80 µs Series Input Resistance Measured from IIN to IOUT — 1.3 — m Ω Series Inductance Measured from IIN to IOUT — 2 — nH Input/Output Delay OUT, OUT1, OUT2 delay relative to input — 50 100 ns Start-Up Self-Cal Delay (tCAL) Time from VDD = VUVLO + VHYST to cal complete — 150 200 µs Input Common Mode Voltage Range — — 1,000 V Operating Input Frequency Range (f) 50 — 1,200 kHz DC Power Supply Rejection Ratio — 80 — db Sensitivity Si85x1/4/7 — 400 — mV/A Si85x2/5/8 — 200 — mV/A Si85x3/6/9 — 100 — mV/A OUT, OUT1, OUT2 Offset Voltage (VOUTMIN) Current flow from IIN to IOUT = 0 — 10 — mV VOUT Slew Rate OUT, OUT1, OUT2 load = 5K || 50 pF — 50 — V/µs OUT, OUT1, OUT2 Output Resistance 20 30 Ω Measurement Error (%)—all devices (–40 to 85 ºC Temp Range) 5 to 10% of full scale –20 — +20 % 10 to 20% of full scale –10 — +10 % 20 to 100% of full scale –5 — +5 % |
类似零件编号 - SI8502-B-GM |
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类似说明 - SI8502-B-GM |
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