CY14B104L/CY14B104N
PRELIMINARY
Document #: 001-07102 Rev. *E
Page 3 of 21
Pin Definitions
Pin Name
IO Type
Description
A0 – A16
Input
Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
DQ0 – DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, enables data on the IO pins to be written
to the address location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE high.
VSS
Ground
Ground For The Device. Must be connected to ground of the system.
VCC
Power Supply Power Supply Inputs To The Device.
HSB
Input Output Hardware Store Busy (HSB). When low this output indicates a hardware store is in progress. When
pulled low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected. (connection optional)
VCAP
Power Supply Autostore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No Connect
No Connect. Do not connect this pin to the die.
Pin Configurations (continued)
A17
DQ7
DQ6
DQ5
DQ4
VCC
DQ3
DQ2
DQ1
DQ0
NC
A0
A1
A2
A3
A4
A5
A6
A7
VCAP
WE
A8
A10
A11
A12
A13
A14
A15
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(not to scale)
OE
CE
VCC
NC
VSS
NC
A9
NC
NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
(x16)
[1]
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