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STAC9758 数据表(PDF) 2 Page - Integrated Device Technology |
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STAC9758 数据表(HTML) 2 Page - Integrated Device Technology |
2 / 119 page STAC9758/9759 HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™ PC AUDIO IDT™ 2 STAC9758/9759 V 1.2 1206 HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™ TABLE OF CONTENTS 1. DESCRIPTION ........................................................................................................................... 7 1.1. Features ........................................................................................................................................... 8 1.2. Block Diagram ................................................................................................................................... 9 2. CHARACTERISTICS/SPECIFICATIONS ................................................................................10 2.1. Electrical Specifications ................................................................................................................... 10 2.1.1. Absolute Maximum Ratings ............................................................................................... 10 2.1.2. Recommended Operation Conditions ............................................................................... 10 2.1.3. Power Consumption ......................................................................................................... 11 2.1.4. AC-Link Static Digital Specifications ................................................................................. 12 2.1.5. STAC9758 5V Analog Performance Characteristics ........................................................12 2.1.6. STAC9759 3.3V Analog Performance Characteristics .....................................................14 2.2. AC Timing Characteristics ............................................................................................................... 17 2.2.1. Cold Reset ......................................................................................................................... 17 2.2.2. Warm Reset ....................................................................................................................... 17 2.2.3. Clocks ................................................................................................................................ 18 2.2.4. STAC9758/9759 Crystal Elimination Circuit and Clock Frequencies ................................19 2.2.5. Data Setup and Hold ........................................................................................................ 20 2.2.6. Signal Rise and Fall Times ................................................................................................ 20 2.2.7. AC-Link Low Power Mode Timing ..................................................................................... 21 2.2.8. ATE Test Mode ..................................................................................................................21 3. TYPICAL CONNECTION DIAGRAM .......................................................................................22 3.1. Split Independent Power Supply Operation .................................................................................... 23 4. CONTROLLER, CODEC AND AC-LINK .................................................................................25 4.1. AC-Link Physical interface ............................................................................................................... 25 4.2. Controller to Single CODEC ............................................................................................................ 25 4.3. Controller to Multiple CODECs ........................................................................................................ 27 4.3.1. Primary CODEC Addressing ............................................................................................. 27 4.3.2. Secondary CODEC Addressing ........................................................................................ 27 4.3.3. CODEC ID Strapping ......................................................................................................... 28 4.4. Clocking for Multiple CODEC Implementations ............................................................................... 28 4.5. STAC9758/9759 as a Primary CODEC ........................................................................................... 28 4.5.1. STAC9758/9759 as a Secondary CODEC ........................................................................ 28 4.6. AC-Link Power Management ........................................................................................................... 29 4.6.1. Powering down the AC-Link .............................................................................................. 29 4.6.2. Waking up the AC-Link ...................................................................................................... 29 4.6.3. CODEC Reset ................................................................................................................... 30 5. AC-LINK DIGITAL INTERFACE ..............................................................................................31 5.1. Overview ......................................................................................................................................... 31 5.2. AC-Link Serial Interface Protocol .................................................................................................... 32 5.2.1. AC-Link Variable Sample Rate Operation ......................................................................... 33 5.2.2. Variable Sample Rate Signaling Protocol .......................................................................... 33 5.2.3. Primary and Secondary CODEC Register Addressing ...................................................... 34 5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 35 5.3.1. Slot 0: TAG / CODEC ID ................................................................................................... 36 5.3.2. Slot 1: Command Address Port ......................................................................................... 36 5.3.3. Slot 2: Command Data Port ............................................................................................... 37 5.3.4. Slot 3: PCM Playback Left Channel .................................................................................. 37 5.3.5. Slot 4: PCM Playback Right Channel ................................................................................ 37 5.3.6. Slot 5: Modem Line 1 Output Channel .............................................................................. 37 5.3.7. Slot 6 - 11: DAC ................................................................................................................. 37 5.3.8. Slot 12: Audio GPIO Control Channel ............................................................................... 38 5.4. AC-Link Input Frame (SDATA_IN) ................................................................................................. 38 5.4.1. Slot 0: TAG ........................................................................................................................39 |
类似零件编号 - STAC9758 |
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类似说明 - STAC9758 |
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