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IDTCSPU877D 数据表(PDF) 3 Page - Integrated Device Technology |
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IDTCSPU877D 数据表(HTML) 3 Page - Integrated Device Technology |
3 / 13 page 3 IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIALTEMPERATURERANGE ABSOLUTE MAXIMUM RATINGS(1,2) Symbol Rating Max Unit VDDQ, AVDD SupplyVoltageRange –0.5 to +2.5 V VI(3) InputVoltageRange –0.5 to VDDQ + 0.5 V VO(3) Voltagerangeappliedtoany –0.5 to VDDQ + 0.5 V output in the high or low state IIK Input clamp current ±50 mA (VI <0) IOK Output Clamp Current ±50 mA (VO <0 or VO > VDDQ) IO Continuous Output Current ±50 mA (VO =0 to VDDQ) VDDQ or GND Continuous Current ±100 mA TSTG Storage Temperature Range – 65 to +150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit AVDD(1) SupplyVoltage VDDQ V VDDQ I/O Supply Voltage 1.7 1.8 1.9 V TA OperatingFree-AirTemperature 0 +70 °C CAPACITANCE(1) Parameter Description Min. Typ. Max. Unit CIN Input Capacitance 2 — 3 pF VI = VDDQ or GND CI ∆ DeltaInputCapacitance 0.25 pF CLK, CLK, FBIN, FBIN CL LoadCapacitance — 10 — pF NOTE: 1. Unused inputs must be held high or low to prevent them from floating. VDDQ Y7 FBIN FBIN FBOUT 30 29 28 27 26 25 24 23 22 21 FBOUT OE OS Y7 VDDQ GND VDDQ Y2 Y2 AGND AVDD CLK CLK VDDQ 2 3 4 5 6 7 8 1 9 10 VDDQ GND MLF TOP VIEW NOTE: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are guaranteed. PIN CONFIGURATION |
类似零件编号 - IDTCSPU877D |
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类似说明 - IDTCSPU877D |
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