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CS5340-DZZ 数据表(PDF) 3 Page - Cirrus Logic |
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CS5340-DZZ 数据表(HTML) 3 Page - Cirrus Logic |
3 / 22 page DS601F1 3 CS5340 LIST OF FIGURES Figure 1.Single-Speed Mode Stopband Rejection ...................................................................................... 8 Figure 2.Single-Speed Mode Stopband Rejection ...................................................................................... 8 Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8 Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8 Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8 Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8 Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9 Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9 Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9 Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9 Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9 Figure 12.Quad-Speed Mode Passband Ripple ......................................................................................... 9 Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12 Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12 Figure 15.Master Mode, I²S SAI ................................................................................................................ 12 Figure 16.Slave Mode, I²S SAI .................................................................................................................. 12 Figure 17.Typical Connection Diagram ..................................................................................................... 14 Figure 18.CS5340 Master Mode Clocking ................................................................................................ 16 Figure 19.I²S Serial Audio Interface .......................................................................................................... 17 Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17 Figure 21.CS5340 Recommended Analog Input Buffer ............................................................................ 18 Figure 22.CS5340 THD+N versus Frequency .......................................................................................... 19 LIST OF TABLES Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 15 Table 2. CS5340 Mode Control ................................................................................................................. 15 Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17 Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17 |
类似零件编号 - CS5340-DZZ |
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类似说明 - CS5340-DZZ |
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