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CS5321 数据表(PDF) 10 Page - Cirrus Logic |
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CS5321 数据表(HTML) 10 Page - Cirrus Logic |
10 / 36 page CS5321/22 10 DS454F3 CS5322 POWER SUPPLY (T A = (See Note 1); VD+ = 5 V; CLKIN = 1.024 MHz) CS5322 SWITCHING CHARACTERISTICS (T A = (See Note 1); VD+ = 5 V ± 5%; DGND = 0 V; Inputs: Logic 0 = 0 V Logic 1 = VD+; CL = 50 pF (Note 23) 23. Guaranteed by design, characterization and/or test. Parameter CS5322-BL Min Typ Max Unit Power Supply Current: ID+ (Note 11) - 2.2 4 mA Power Dissipation: (Note 11) PWDN Low PWDN High - - 11 0.6 20 2.5 mW mW Parameter Symbol Min Typ Max Units CLKIN Frequency fc 0.512 1.024 1.2 MHz CLKIN Duty Cycle 40 - 60 % Rise Times: Any Digital Input Any Digital Output trise - - - 50 100 100 ns ns Fall Times: Any Digital Input Any Digital Output tfall - - - 50 100 100 ns ns Serial Port Read Timing DRDY to Data Valid tddv - - 25 ns RSEL Setup Time before Data Valid trss 50 - - ns Read Setup before CS Active trsc 20 - - ns Read Active to Data Valid trdv - - 50 ns SCLK rising to New SOD bit trdd - - 50 ns SCLK Pulse Width High trph 30 - - ns SCLK Pulse Width Low trpl 30 - - ns SCLK Period trsp 100 - - ns SCLK falling to DRDY falling trst - - 50 ns CS High to Output Hi-Z trch - - 20 ns Read Hold Time after CS Inactive trhc 20 - - ns Read Select Setup to SCLK falling trds 20 - - ns Serial Port Write Timing Write Setup Before CS Active twsc 20 - - ns SCLK Pulse Width Low twpl 30 - - ns SCLK Pulse Width High twph 30 - - ns SCLK Period twsp 100 - - ns Write Setup Time to First SCLK falling twws 20 - - ns Data Setup Time to First SCLK falling twds 20 - - ns Write Select Hold Time after SCLK falling twwh 20 - - ns Write Hold Time after CS Inactive twhc 20 - - ns Data Hold Time after SCLK falling twdh 20 - - ns |
类似零件编号 - CS5321_06 |
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类似说明 - CS5321_06 |
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