 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS4362 数据表(PDF) 11 Page - Cirrus Logic |
|
||||||||||||||||||||||||||||||
CS4362 数据表(HTML) 11 Page - Cirrus Logic |
|
|
11 / 42 page  CS4362 DS257F1 11 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For KQZ TA = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF) Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For FSCK < 1 MHz. Parameter Symbol Min Max Unit CCLK Clock Frequency fsclk -MHz RST Rising Edge to CS Falling tsrs 500 - ns CCLK Edge to CS Falling (Note 22) tspi 500 - ns CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl -ns CCLK High Time tsch -ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 23) tdh 15 - ns Rise Time of CCLK and CDIN (Note 24) tr2 -100 ns Fall Time of CCLK and CDIN (Note 24) tf2 -100 ns MCLK 2 ------------------ 1 MCLK ------------------ 1 MCLK ------------------ t r2 t f2 t dsu t dh t sch t scl CS CC L K CD IN t css t csh t spi t srs RS T Figure 4. Control Port Timing - SPI Format |
类似零件编号 - CS4362_04 |
|
类似说明 - CS4362_04 |
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
