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MAX5075 数据表(PDF) 6 Page - Maxim Integrated Products |
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MAX5075 数据表(HTML) 6 Page - Maxim Integrated Products |
6 / 8 page Detailed Description The MAX5075 is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator for use in 48V module power supplies. The MAX5075 features a programmable, accurate inte- grated oscillator with a synchronizing clock output that can be used to synchronize an external PWM stage. A single external resistor programs the internal oscillator frequency from 50kHz to 1.5MHz. The MAX5075 incorporates a dual MOSFET driver with ±3A peak drive currents and a 50% duty cycle. The MOSFET driver generates complementary signals to drive external ground-referenced n-channel MOSFETs. The MAX5075 is available with a clock output frequency to MOSFET driver frequency ratios of 1x , 2x, and 4x. Internal Oscillator An external resistor at RT programs the MAX5075 internal oscillator frequency from 50kHz to 1.5MHz. The MAX5075A/B NDRV1 and NDRV2 switching frequen- cies are one-half the programmed oscillator frequency with a nominal 50% duty cycle. The MAX5075C NDRV1 and NDRV2 switching frequencies are one-fourth the oscillator frequency. Use the following formula to calculate the internal oscil- lator frequency: where fOSC is the oscillator frequency and RRT is a resistor connected from RT to DGND in ohms. Place a series combination of a 4.7kΩ resistor and a 1nF capacitor from RT to DGND for stability and to filter out noise. Synchronizing Clock Output The MAX5075 provides a buffered clock output that can be used to synchronize the oscillator input of a PWM con- troller. CLK is powered from an internal 5V regulator and sources/sinks up to 10mA. The MAX5075 has internal CLK output frequency to NDRV1 and NDRV2 switching frequency ratios set to 1x, 2x, or 4x (Table 1). The MAX5075A has a CLK frequency to NDRV_ frequen- cy ratio set to 1x. The MAX5075B has a CLK frequency to NDRV_ frequency ratio set to 2x and the MAX5075C has a CLK frequency to NDRV_ frequency ratio set to 4x. There is a typical 30ns delay from CLK to NDRV_ output. Applications Information Supply Bypassing Pay careful attention to bypassing and grounding the MAX5075. Peak supply and output currents may exceed 3A when driving large MOSFETs. Ground shifts due to insufficient device grounding may also disturb other cir- cuits sharing the same ground-return path. Any series inductance in the VCC, NDRV1, NDRV2, and/or GND paths can cause noise due to the very high di/dt when switching the MAX5075 with any capacitive load. Place one or more 0.1µF ceramic capacitors in parallel as close to the device as possible to bypass VCC to PGND. Use a ground plane to minimize ground-return resistance and inductance. Place the external MOSFETs as close as possible to the MAX5075 to further minimize board induc- tance and AC path impedance. f xR OSC RT = 10 32 12 Push-Pull FET Driver with Integrated Oscillator and Clock Output 6 _______________________________________________________________________________________ PART fCLK fNDRV1 fCLK to fSW RATIO MAX5075A fOSC / 2 fOSC / 2 1 MAX5075B fOSC fOSC / 2 2 MAX5075C fOSC fOSC / 4 4 Table 1. MAX5075 CLK Output Frequency CLK OSC NDRV1 NDRV2 CLK OSC NDRV1 NDRV2 CLK OSC NDRV1 NDRV2 MAX5075A MAX5075B MAX5075C Figure 2. MAX5075 CLK Timing Diagrams |
类似零件编号 - MAX5075_07 |
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类似说明 - MAX5075_07 |
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