TDA9840T datasheet(7/28 Pages) PHILIPS

部件名	TDA9840T

功能描述	TV and VTR stereo/dual sound processor with digital identification and I2C-bus control

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制造商	PHILIPS [NXP Semiconductors]

网页	http://www.nxp.com

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7 / 28 page

1998 Jul 03

7

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I2C-bus control

TDA9840

FUNCTIONAL DESCRIPTION

The TDA9840 (see Fig.1) receives the signals from the

FM-demodulators in a TV two sound-carrier system. The

circuit is realized by the H00485 bipolar process.

The IC is intended for use in economic TV and VTR

receivers. Therefore optimum relationship between

integration of functions and use of external components

has been striven for. Additionally a new type of

identification circuit has been developed.

AF signal handling

The input AF signals, derived from the two sound carriers,

are processed in analog form using operational

amplifiers.The circuit incorporates level- and

stereo-adjustment to correct the spreading in the FM

detector output levels. Dematrixing uses the technique of

two amplifiers processing the AF signals. Finally, a source

selector provides the facility to route the mono signal

through to the outputs (‘forced mono’).

De-emphasis is performed by two RC low-pass filter

networks with internal resistors and external capacitors.

This provides a frequency response with the tolerances

given in Fig.4.

A source selector, controlled via the I2C-bus, allows

selection of the different modes of operation in accordance

with the transmitted signal. The device was designed for a

nominal input signal (FM: 54% modulation is equivalent to

∆f= ±27 kHz / AM: m = 0.54) of 250 mV RMS (Vi1,Vi2),

respectively 500 mV RMS (Vi3,Vi4). A nominal gain of

6 dB for Vi1 and Vi2 signals and 0 dB for Vi3 and Vi4

signals is built-in. By using rail-to-rail operational

amplifiers, the clipping level (THD

≤1.5%) is 1.6 V RMS for

VP = 5 V and 2.65 V RMS for VP = 8 V at outputs Vo1,

Vo2,Vo3 and Vo4. Care has been taken to minimize

switching plops. Also total harmonic distortion and random

noise are considerably reduced.

Identiﬁcation

The pilot signal is fed via an external RC high-pass filter

and single tuned LC band-pass filter to the input of a gain

controlled amplifier. The external LC band-pass filter in

combination with the external RC high-pass filter should

have a loaded Q-factor of about 40 to 50 to ensure the

highest identification sensitivity. By using a fixed coil (

±5%)

to save the alignment (see Fig.2), a Q-factor of about 12 is

proposed. This may cause a loss in sensitivity of about

2 to 3 dB. A digital PLL circuit generates a reference

carrier, which is synchronized with the pilot carrier.

This reference carrier and the gain controlled pilot signal

are fed to the AM-synchronous demodulator. The

demodulator detects the identification signal, which is fed

through a low-pass filter with external capacitor CLP (pin 3)

to a Schmitt-trigger for pulse shaping and suppression of

low level spurious signal components. This is a measure

against mis-identification.

The identification signal is amplified and fed through an

AGC low-pass filter with external capacitor CAGC (pin 2) to

obtain the AGC voltage for controlling the gain of the pilot

signal amplifier.

The identification stages consist of two digital PLL circuits

with digital synchronous demodulation and digital

integrators to generate the stereo or dual sound

identification bits which can be read out via the I2C-bus.

A 10 MHz quartz crystal oscillator provides the reference

clock frequency. The corresponding detection bandwidth

is larger than

±50 Hz for the pilot carrier signal, so that

fp-variations from the transmitter can be tracked in case of

missing synchronisation with the horizontal frequency fH.

However the detection bandwidth for the identification

signal is made small (approximately

±1 Hz) to reduce

mis-identification.

Figure 2 shows an example of the alignment-free fp

band-pass filter. To achieve the required QL of

approximately 12, the Q0 at fp of the coil was chosen to be

approximately 25 (effective Q0 including PCB influence).

Using coils with other Q0, the RC-network (RFP,CFP) has

to be adapted accordingly. It is assumed that the loss

factor tan

δ of the resonance capacitor is ≤0.01 at fp.

Copper areas under the coil might influence the loaded Q

and have to be taken into account. Care has also to be

taken in environments with strong magnetic fields when

using coils without magnetic shielding.

I2C-bus transceiver

The complete IC is controlled by a microcomputer via the

I2C-bus. The built-in I2C-bus transceiver transmits the

identification result to the I2C-bus and receives the control

data for the source selector and level control. The I2C-bus

protocol is given in Tables 2 to 12 respectively.

The data transmission between the microcontroller and

the other I2C-bus controlled ICs is not disturbed, when the

supply voltage of the TDA9840 is not connected or when

powering up or down. Finally, a Schmitt-trigger is built-in

the SDA/SCL interface to suppress spikes from the

I2C-bus.

类似零件编号 - TDA9840T

制造商	部件名	数据表	功能描述
NXP Semiconductors	TDA9845	177Kb / 20P	TV and VTR stereo/dual sound processor with digital identification 1995 Mar 20
	TDA9845T	177Kb / 20P	TV and VTR stereo/dual sound processor with digital identification 1995 Mar 20
	TDA9847	147Kb / 28P	TV and VTR stereo/dual sound processor with digital identification 1995 May 23
	TDA9847T	147Kb / 28P	TV and VTR stereo/dual sound processor with digital identification 1995 May 23

More results

类似说明 - TDA9840T

制造商	部件名	数据表	功能描述
NXP Semiconductors	TDA9845	177Kb / 20P	TV and VTR stereo/dual sound processor with digital identification 1995 Mar 20
	TDA9847	147Kb / 28P	TV and VTR stereo/dual sound processor with digital identification 1995 May 23
	TDA8405	322Kb / 9P	TV AND VTR STEREO/DUAL SOUND PROCESSOR WITH I2C BUS CONTROL December 1985
	TDA8415	128Kb / 19P	TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control May 1989
	TDA8416	134Kb / 19P	TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control November 1989
	TDA8417	130Kb / 20P	TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control September 1989
	TDA2795	236Kb / 6P	TV STEREO / DUAL SOUND IDENTIFICATION DECODER March 1986
Sony Corporation	CXA2022S	257Kb / 16P	I2C Bus Sound Processor for TV
Sony Corporation	CXA2021S	274Kb / 16P	I2C BUS Sound Processor for TV
NEC	UPC1857A	343Kb / 44P	SOUND CONTROL IC WITH SURROUND AND I2C BUS