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TDA9144 数据表(PDF) 7 Page - NXP Semiconductors

部件名 TDA9144
功能描述  I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Download  44 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

TDA9144 数据表(HTML) 7 Page - NXP Semiconductors

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1996 Jan 17
7
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
TDA9144
Fig.3 Search loop of the identification circuit.
handbook, full pagewidth
PAL
KILLED
PAL
KILLED
PAL
KILLED
NTSC
KILLED
NTSC
KILLED
SECAM
KILLED
Reference crystal
Second crystal
MGE040
PAL
NTSC
NTSC
PAL
SECAM
c
c
c
c
c
c
c
c
c
c
c
Integrated filters
All chrominance bandpass and notch filters, including the
luminance delay line, are an integral part of the IC. The
filters are gyrator-capacitor type filters. The resonant
frequency of the filters is controlled by a circuit that uses
the active crystal to tune the SECAM Cloche filter during
the vertical flyback time. The remaining filters and the
luminance delay line are matched to this filter. The filters
can be switched to either 4.43 MHz, 4.29 MHz or
3.58 MHz. The switching is controlled by the standard
identification circuit. The luminance notch used for
SECAM has a lower Q-factor than the notch used for
PAL/NTSC. The notches are provided with a little preshoot
to obtain a symmetrical step response. In Y/C mode the
chrominance notch filters are bypassed, to preserve full
signal bandwidth. For a CVBS signal the chrominance
notch filters can be bypassed by bus selection of bit TB
(trap bypass).
The luminance to helper delay difference can be adjusted
by I2C-bus, to achieve a correct fitting for the delay in the
PALplus helper demodulation signal path and the
luminance path (not for helper only with trap). The delay of
the colour difference signals
−(R−Y) and −(B−Y) in the
chrominance signal path and the external chrominance
delay lines when used, can be fitted to the luminance
signal delay control via I2C-bus in 40 ns steps.
The typical luminance delay can be calculated:
delay
≈ 90 + SAK⋅SBK {170 + 40(FRQ⋅TB)} + 160(YD3) +
160(YD2) + 80(YD1) + 40(YD0) [ns].


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