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TDA8798HL 数据表(PDF) 5 Page - NXP Semiconductors

部件名 TDA8798HL
功能描述  Dual 8-bit, 100 Msps A/D converter with DPGA
Download  24 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

TDA8798HL 数据表(HTML) 5 Page - NXP Semiconductors

  TDA8798HL Datasheet HTML 1Page - NXP Semiconductors TDA8798HL Datasheet HTML 2Page - NXP Semiconductors TDA8798HL Datasheet HTML 3Page - NXP Semiconductors TDA8798HL Datasheet HTML 4Page - NXP Semiconductors TDA8798HL Datasheet HTML 5Page - NXP Semiconductors TDA8798HL Datasheet HTML 6Page - NXP Semiconductors TDA8798HL Datasheet HTML 7Page - NXP Semiconductors TDA8798HL Datasheet HTML 8Page - NXP Semiconductors TDA8798HL Datasheet HTML 9Page - NXP Semiconductors Next Button
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1999 Sep 16
5
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
BUF1
17
buffer1 non-inverting input
BUF1N
18
buffer1 inverting input
Voref1
19
buffer1 common mode reference output
VDDA3
20
ADC1 analog supply voltage 3
VSSA3
21
ADC1 analog ground 3
CLK1N
22
ADC1 inverting clock input
CLK1
23
ADC1 non-inverting clock input
VSSD1
24
digital ground 1
VDDD1
25
digital supply voltage 1
SMODE
26
serial interface mode input
SEN2
27
serial interface enable 2 (active low)
SDATA
28
serial interface data input
SCLK
29
serial interface clock input
SEN1
30
serial interface enable 1 (active low)
VDDO1
31
output stage supply voltage 1
VSSO1
32
output stage ground 1
A7
33
channel 1 output bit 7 (MSB)
A6
34
channel 1 output bit 6
A5
35
channel 1 output bit 5
A4
36
channel 1 output bit 4
A3
37
channel 1 output bit 3
A2
38
channel 1 output bit 2
A1
39
channel 1 output bit 1
A0
40
channel 1 output bit 0 (LSB)
B0
41
channel 2 output bit 0 (LSB)
B1
42
channel 2 output bit 1
B2
43
channel 2 output bit 2
B3
44
channel 2 output bit 3
B4
45
channel 2 output bit 4
B5
46
channel 2 output bit 5
B6
47
channel 2 output bit 6
B7
48
channel 2 output bit 7 (MSB)
VSSO2
49
output stage ground 2
VDDO2
50
output stage supply voltage 2
OE
51
digital output enable (active LOW)
SR
52
digital output bit slew-rate control
DPGAEN
53
DPGA enable (active LOW)
TEST
54
test input (to be grounded)
TE
55
track-and-hold enable (active LOW)
VDDD2
56
digital supply voltage 2
VSSD2
57
digital ground 2
SYMBOL
PIN
DESCRIPTION


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