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STK14D88-NF35ITR 数据表(PDF) 5 Page - Simtek Corporation |
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STK14D88-NF35ITR 数据表(HTML) 5 Page - Simtek Corporation |
5 / 19 page STK14D88 5 February 2007 Document Control #ML0033 Rev 1.7 SRAM READ CYCLES #1 & #2 Note c: W must be high during SRAM READ cycles. Note d: Device is continuously selected with E and G both low Note e: Measured ± 200mV from steady state output voltage. Note f: HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f SRAM READ CYCLE #2: E Controlledc,f NO. SYMBOLS PARAMETER STK14D88-25 STK14D88-35 STK14D88-45 UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX 1 tELQV tACS Chip Enable Access Time 25 35 45 ns 2 tAVAVc tAVAVc tRC Read Cycle Time 25 35 45 ns 3 tAVQVd tAVQVd tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 12 15 20 ns 5 tAXQXd tAXQXd tOH Output Hold after Address Change 3 3 3 ns 6 tELQX tLZ Chip Enable to Output Active 3 3 3 ns 7 tEHQZe tHZ Chip Disable to Output Inactive 10 13 15 ns 8 tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9 tGHQZe tOHZ Output Disable to Output Inactive 10 13 15 ns 10 tELICCHb tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICCLb tPS Chip Disable to Power Standby 25 35 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQX STANDBY DATA VALID 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 10 tELICCH 11 tEHICCL 7 tEHQZ 8 tGLQX 1 tELQV 9 tGHQZ |
类似零件编号 - STK14D88-NF35ITR |
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类似说明 - STK14D88-NF35ITR |
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