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DAC8871 Datasheet(数据表) 5 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
部件型号  DAC8871
说明  16-Bit, Single-Channel, ±18V Output (Unbuffered), Ultra-Low Power, Serial Interface DIGITAL-TO-ANALOG CONVERTER
下载  19 Pages
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制造商  BURR-BROWN [Burr-Brown (TI)]
网页  http://www.burr-brown.com
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PIN CONFIGURATION (NOT TO SCALE)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DGND
LDAC
SDI
SCLK
CS
RST
RSTSEL
V
DD
V
OUT
V
CC
V
SS
AGND
V
-F
REFH
V
-S
REFH
V
-S
REFL
V
-F
REFL
DAC8871
DAC8871
SBAS396 – JUNE 2007
PW PACKAGE
TSSOP-16
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO.
NAME
1
VOUT
Analog output of the DAC
2
VCC
Positive analog power supply: +15V
3
VSS
Negative analog power supply: –15V
4
AGND
Analog ground
5
VREFH-F
VREFH reference input (Force). Connect to external VREFH.
6
VREFH-S
VREFH reference input (Sense). Connect to external VREFH.
7
VREFL-S
VREFL reference input (Sense). Connect to external VREFL.
8
VREFL-F
VREFL reference input (Force). Connect to external VREFL.
9
VDD
Digital power. +5V for 5V interface logic; +3V for 3V logic.
Power-On-Reset select. Determines VOUT after power-on reset. If tied to VDD, the DAC latch is set to mid-scale
10
RSTSEL
after power-on, and VOUT is (VREFH– VREFL)/2. If tied to DGND, the DAC latch is cleared ('0'), and VOUT is VREFL.
11
RST
Reset (active low)
12
CS
Chip select input (active low). Data are not clocked into SDI unless CS is low.
13
SCLK
Serial clock input
14
SDI
Serial data input. Data are latched into input register on the rising edge of SCLK.
Load DAC control input (active low). When LDAC is low, the DAC latch is simultaneously updated with the content
15
LDAC
of the input register.
16
DGND
Digital ground
5
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