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DS3100 数据表(PDF) 21 Page - Maxim Integrated Products |
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DS3100 数据表(HTML) 21 Page - Maxim Integrated Products |
21 / 226 page DS3100 Stratum 3/3E Timing Card IC 21 of 226 Table 6-7. SPI Bus Mode Pin Descriptions Note: These pins are active in SPI interface modes. See Section 7.12.2 for functional description and Section 10.6 for timing specifications. PIN NAME (1) TYPE (2) FUNCTION J16 CS IPU Active-Low Chip Select. This pin must be asserted to read or write internal registers. C16 SCLK I Serial Clock. SCLK is always driven by the SPI bus master. D16 SDI I Serial Data Input. The SPI bus master transmits data to the device on this pin. E15 SDO O Serial Data Output. The device transmits data to the SPI bus master on this pin. D14 CPHA I Clock Phase. See Figure 7-18. 0 = data is latched on the leading edge of the SCLK pulse 1 = data is latched on the trailing edge of the SCLK pulse C14 CPOL I Clock Polarity. See Figure 7-18. 0 = SCLK is normally low and pulses high during bus transactions 1 = SCLK is normally high and pulses low during bus transactions A15 INTREQ O Interrupt Request. The behavior of this pin is configured in the INTCR register. Polarity can be active high or active low. Drive action can be push-pull or open drain. The pin can also be configured as a general-purpose output if the interrupt request function is not needed. Table 6-8. JTAG Interface Pin Descriptions Note: See Section 9 for functional description and Section 10.7 for timing specifications. PIN NAME (1) TYPE (2) FUNCTION T8 JTRST IPU Active-Low JTAG Test Reset. Asynchronously resets the test access port (TAP) controller. If not used, JTRST can be held low or high. R8 JTCLK I JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK can be held low or high. R9 JTDI IPU JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used, JTDI can be held low or high. P9 JTDO O JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used, leave floating. T9 JTMS IPU JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If not used, connect to VDDIO or leave floating. Table 6-9. General-Purpose I/O Pin Descriptions PIN NAME (1) TYPE (2) FUNCTION E2 GPIO1 I/O General-Purpose I/O Pin 1. GPCR:GPIO1D configures this pin as an input or an output. GPCR:GPIO1O specifies the output value. GPSR:GPIO1 indicates the state of the pin. F3 GPIO2 I/O General-Purpose I/O Pin 2. GPCR:GPIO2D configures this pin as an input or an output. GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of the pin. H2 GPIO3 I/O General-Purpose I/O Pin 3. GPCR:GPIO3D configures this pin as an input or an output. GPCR:GPIO3O specifies the output value. GPSR:GPIO3 indicates the state of the pin. J1 GPIO4 I/O General-Purpose I/O Pin 4. GPCR:GPIO4D configures this pin as an input or an output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates the state of the pin. |
类似零件编号 - DS3100 |
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类似说明 - DS3100 |
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