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LTC1159CG 数据表(PDF) 6 Page - Linear Technology

部件名 LTC1159CG
功能描述  High Efficiency Synchronous Step-Down Switching Regulators
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC1159CG 数据表(HTML) 6 Page - Linear Technology

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6
LTC1159
LTC1159-3.3/LTC1159-5
Internal divider broken at VFB for adjustable versions.
+
N-GATE
P-DRIVE
VCC
550k
P-GATE
PGND
550k
CAP
LOW DROP SWITCH
VCC
EXTVCC
SHDN2
VIN
SENSE+
V
R
S
Q
VTH1
25mV TO 150mV
13k
G
REFERENCE
1.25V
SGND
ITH
C
VOS
SENSE
LTC1159 • FD
SHDN1
T
VTH2
S
SLEEP
CT
VFB
OFF-TIME
CONTROL
SENSE
LOW DROPOUT
4.5V REGULATOR
100k
FU CTIO AL DIAGRA
The LTC1159 uses a current mode, constant off-time
architecture to synchronously switch an external pair of
complementary power MOSFETs. Operating frequency is
set by an external capacitor at the CT pin.
The output voltage is sensed either by an internal voltage
divider connected to the SENSE pin (LTC1159-3.3 and
LTC1159-5) or an external divider returned to the VFB pin
(LTC1159). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference volt-
age of 1.25V. To optimize efficiency, the LTC1159 auto-
matically switches between two modes of operation, burst
and continuous.
A low dropout 4.5V regulator provides the operating volt-
age VCC fortheMOSFETdriversandcontrolcircuitryduring
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the
EXTVCC pin to improve efficiency. The N-GATE pin is
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input VIN, which is accomplished by
level-shifting the P-drive signal via an internal 550k resistor
and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between the SENSE+
and SENSEpins connected across an external shunt in
series with the inductor. When the voltage across the shunt
reaches its threshold value, the P-gate output is switched
to VIN, turning off the P-channel MOSFET. The timing
capacitor CT is now allowed to discharge at a rate deter-
mined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
capacitor is discharging, the N-gate output is high, turning
on the N-channel MOSFET.
When the voltage on CThasdischargedpastVTH1,compara-
tor T trips, setting the flip-flop. This causes the N-gate output
to go low (turning off the N-channel MOSFET) and the P-
gate output to also go low (turning the P-channel MOSFET
back on). The cycle then repeats. As the load current
(Refer to Functional Diagram)
OPERATIO


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