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LT1036 数据表(PDF) 6 Page - Linear Technology |
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LT1036 数据表(HTML) 6 Page - Linear Technology |
6 / 12 page 6 LT1036 1036fa Figure 1 Figure 2 Figure 3 The basic shutdown control circuit uses a direct gate drive or an open collector driver and a pull-up resistor which are tied to VAUX, as shown in Figure 2. APPLICATIO S I FOR ATIO Driving the Enable Pin The enable pin equivalent schematic is shown in Figure 3. Basically, enable pin current is zero above the threshold and about 1.5 µA below the threshold, flowing out of the pin. Standard logic, such as TTL and CMOS, will interface directly to the enable pin, even if the logic output swing is higher than the input voltage (VIN) to the regulator. 15V CMOS can be used to drive the enable pin, even if the regulator is not powered up, without loading the CMOS output. Timing functions, such as delayed power-up or power-down can be implemented with an RC network. The current flowing out of the enable pin should not be used as the timing current in delayed power-up applications as it is temperature sensitive and varies somewhat from device to device. Instead, a resistor tied to the auxiliary output, the input, or to a logic signal should be used. The timing resistor chosen should provide at least 25 µA of current to “swamp out” the effects of the internal current. Main Output Current Voltage Characteristics Following a high to low transition at the enable pin, the main regulator output will begin to drop after a delay of approximately 0.4 µs. With no capacitive load, the output will fall to zero in approximately 0.8 µs (RL = 4Ω to 100Ω). With a capacitive load, fall time is limited by the RC product of the load and the output capacitance. For light loads (RL>400Ω), the discharge time is controlled by an internal current pull-down of 15mA for output voltages down to 1.5V. Below 1.5V, the pull-down current drops to ≈ 4mA. The DC output voltage in the shutdown mode is approximately 0.12V due to an internal current path in the regulator. (See Figure 4.) The user should note that the output in the low state can only sink about 3mA. If current is forced into the output, the output voltage will rise to 1V at 5mA and about 1.5V at 10mA. With no output capacitor, the rise time of the main output is about 12 µs. With an output capacitor, rise time is limited by the short circuit current of the LT1036 and the load capacitance. A 10 µF output capacitor slows the output rise time to approximately 80 µs. Figure 4 VIN VO 12V 5V + + + LT1036 GND OUT IN 1 4 3 2 5 AUX EN 1 µF 2 µF 2 µF LT1036M/1036C • AI01 7.5-20V 12V 5V V AUX LT1036 GND OUT IN AUX EN LT1036M/1036C • AI02 0mA–75mA LOAD 0A-3A LOAD OUTPUT VOLTAGE (V) 0 0 1 3 4 5 10 7 0.4 0.8 1.0 LT1036M/1036C • AI04 2 8 9 6 0.2 0.6 1.2 1.4 1.6 TJ = 25°C TJ = 150°C TJ = –55°C VIN = 15V ENABLE 1V 70 µA LT1036M/1036C • AI03 |
类似零件编号 - LT1036 |
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类似说明 - LT1036 |
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