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TDA10085 数据表(PDF) 5 Page - NXP Semiconductors

部件名 TDA10085
功能描述  Single chip DVB-S/DSS channel receiver
Download  16 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

TDA10085 数据表(HTML) 5 Page - NXP Semiconductors

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2001 Aug 31
5
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
XIN
1
I
crystal oscillator input and output pins; in a typical application, a
fundamental oscillator crystal is connected between pins XIN and
XOUT; see note 1
XOUT
2
I
VDDI
3
supply
digital core supply voltage (typically 1.8 V)
PLLVCC
4
supply
analog supply voltage for the PLL (typically 3.3 V)
PLLGND
5
ground
analog ground for the PLL
DGND
6
ground
digital PLL core ground voltage; see note 2
DVCC
7
supply
digital PLL core supply voltage (typically 1.8 V)
VDDI
8
supply
digital ADC supply voltage (typically 1.8 V)
VSSI
9
ground
digital ADC ground voltage; see note 2
VDD3
10
supply
analog ADC supply voltage (typically 3.3 V)
AVS
11
ground
analog ground voltage
VIN2
12
I
analog signal input for channel Q; see note 1
VREFN
13
O
negative analog voltage reference output (typically 1.25 V); a
decoupling capacitor (typically 0.1
µF) must be placed as close as
possible between VREFN and GND
VREFP
14
O
positive analog voltage reference output (typically 2 V); a decoupling
capacitor (typically 0.1
µF) must be placed as closed as possible
between VREFP and GND
VIN1
15
I
analog signal input for channel I; see note 1
AVD
16
supply
analog supply voltage (typically 3.3 V); a 0.1
µF decoupling capacitor
must be placed between AVD and AVS
SADDR0
17
I
SADDR0 input signal is the LSB of the I2C-bus address of the
TDA10085; other bits of the address are set internally to 000111,
therefore the complete I2C-bus address is (MSB to LSB):
0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1
TMD
18
I
test input; must be connected to ground for normal operation; see
note 1
ENSERI
19
I
enable serial interface input; when HIGH, the serial transport stream
is present on the boundary scan pins (TRST, TDO, TCK, TDI
and TMS); when LOW, the boundary scan pins are available; note 1
IICDIV
20
I
input to select the I2C-bus internal system clock frequency (depends
on the crystal frequency); internal I2C-bus clock is XIN when
IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1
CTRL1
21
OD
control line output 1; this pin function is directly programmable
through the I2C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
CTRL2
22
OD
control line output 2; this pin function is directly programmable
through the I2C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
VSSE
23
ground
digital ground voltage; see note 2
VDDE5
24
supply
digital 5 V supply voltage; required for the 5 V tolerance of inputs
VSSI
25
ground
digital core ground voltage; see note 2


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