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SAA8122A Datasheet(数据表) 1 Page - NXP Semiconductors

部件型号  SAA8122A
说明  Digital Still Camera Processor ImagIC family
下载  26 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
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SAA8122A Datasheet(HTML) 1 Page - NXP Semiconductors

 
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective specification
c
c
1.
Description
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,
which is dedicated to image processing, compression, formatting and storage. The
DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,
2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy
implementation of a complete system solution and fast development of high
performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments
and connections required for a wide range of Digital Still Cameras. Its embedded
RISC CPU, for which the development environment is available, enables shorter
development and validation cycles, as well as faster feature upgrade. Since one of
the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a
DSP (with advanced embedded algorithm) for camera signal processing is integrated
with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data
compression.
2.
Features
2.1 General
s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),
with RGB Bayer filters up to 2 Mpixels
s Performs an advanced RGB to YUV conversion
s Includes a smart measurement unit to speed up the control loop (focus, auto white
balance, etc.)
s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text
insertion features
s Includes an embedded JPEG encoder/decoder unit
s Includes a MIPS PR3001 CPU, running at a frequency in a range from
12 to 28 MHz
s PRISC compatible PI-bus architecture, interrupt, power management, clock and
reset architectures
s Includes a dedicated video bus supporting SDRAM memory for picture storage




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