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MH32S72VJA-6 数据表(PDF) 1 Page - Mitsubishi Electric Semiconductor

部件名 MH32S72VJA-6
功能描述  2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
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制造商  MITSUBISHI [Mitsubishi Electric Semiconductor]
网页  http://www.mitsubishichips.com
标志 MITSUBISHI - Mitsubishi Electric Semiconductor

MH32S72VJA-6 数据表(HTML) 1 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI
ELECTRIC
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72VJA-6
MITSUBISHI LSIs
8/May. /1999
MIT-DS-0311-0.0
DESCRIPTION
APPLICATION
Main memory or graphic memory in computer systems
PRELIMINARY
Some of contents are subject to change without notice.
1
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
The MH32S72VJA is 33554432 - word x 72-bit Synchronous
DRAM module. This consist of eighteen industry standard
32M x 4 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
5.4ns
(CL = 4 at Latch mode)
MH32S72VJA-6
Utilizes industry standard 32M X 4 Synchronous DRAMs in TSOP
package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Max.
Frequency
Access Time from CLK
[component level]
133MHz
Discrete IC and module design conform to
PC133 specification.


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