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MPC826XZU 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC826XZU 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
22 / 52 page MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 22 Freescale Semiconductor Electrical and Thermal Characteristics Table 12 lists the JTAG timings. NOTE The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge. Table 12. JTAG Timings1 Parameter Symbol2 Min Max Unit Notes JTAG external clock frequency of operation fJTG 025 MHz JTAG external clock cycle time tJTG 40 — ns JTAG external clock pulse width measured at 1.4V tJTKHKL 20 — ns JTAG external clock rise and fall times tJTGR and tJTGF 05 ns 6 TRST assert time tTRST 25 — ns 3, 6 Input setup times Boundary-scan data TMS, TDI tJTDVKH tJTIVKH 4 4 — — ns ns 4, 7 4, 7 Input hold times Boundary-scan data TMS, TDI tJTDXKH tJTIXKH 10 10 — — ns ns 4, 7 4, 7 Output valid times Boundary-scan data TDO tJTKLDV tJTKLOV — — 25 25 ns ns 5, 7 5. 7 Output hold times Boundary-scan data TDO tJTKLDX tJTKLOX 1 1 — — ns ns 5, 7 5, 7 JTAG external clock to output high impedance Boundary-scan data TDO tJTKLDZ tJTKLOZ 1 1 25 25 ns ns 5, 6 5, 6 1 All outputs are measured from the midpoint voltage of the falling/rising edge of t TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2 The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4 Non-JTAG signal input timing with respect to t TCLK. 5 Non-JTAG signal output timing with respect to t TCLK. 6 Guaranteed by design. 7 Guaranteed by design and device characterization. |
类似零件编号 - MPC826XZU |
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类似说明 - MPC826XZU |
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