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MCF5328 数据表(PDF) 5 Page - Freescale Semiconductor, Inc |
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MCF5328 数据表(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 48 page Hardware Design Considerations MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 5 3 Hardware Design Considerations 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible. Figure 2. System PLL VDD Power Filter 3.2 USB Power Filtering To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible. Figure 3. USB VDD Power Filter NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. 3.3 Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 3.3.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is Board IVDD 10 Ω 0.1 µF PLL VDD Pin 10 µF GND Board EVDD 0 Ω 0.1 µF USB VDD Pin 10 µF GND |
类似零件编号 - MCF5328 |
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类似说明 - MCF5328 |
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