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A/Y

B/Z

1.62 k

Ω , ±1%

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V Diff

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

0 V

0 V

R

A

B

SN65MLVD200A, SN65MLVD202A

SN65MLVD204A, SN65MLVD205A

SLLS573 – DECEMBER 2003

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7. Maximum Steady State Output Voltage

A.

All input pulses are supplied by an Agilent 81250 Stimulus System.

B.

The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C.

Period jitter is measured using a 50 MHz 50

±1% duty cycle clock input.

D.

Figure 8. Driver Jitter Measurement Waveforms

Figure 9. Receiver Voltage and Current Definitions

9

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