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AD8118ABPZ 数据表(PDF) 5 Page - Analog Devices |
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AD8118ABPZ 数据表(HTML) 5 Page - Analog Devices |
5 / 36 page AD8117/AD8118 Rev. A | Page 5 of 36 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 2. Limit Parameter Symbol Min Typ Max Unit Serial Data Setup Time t1 40 ns CLK Pulse Width t2 50 ns Serial Data Hold Time t3 50 ns CLK Pulse Separation t4 150 ns CLK to UPDATE Delay t5 10 ns UPDATE Pulse Width t6 90 ns CLK to DATA OUT Valid t7 120 ns Propagation Delay, UPDATE to Switch On or Off 100 ns RESET Pulse Width 60 ns RESET Time 200 ns LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE t2 t4 1 0 CLK 1 0 DATA IN OUT31 (D5) t1 t3 OUT30 (D4) OUT00 (D0) 1 = LATCHED 0 = TRANSPARENT UPDATE TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t5 t7 DATA OUT t6 WE 1 0 Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR, CLK, DATA IN, UPDATE RESET, SER/PAR, CLK, DATA IN, UPDATE DATA OUT DATA OUT RESET1, SER/PAR, CLK, DATA IN, UPDATE RESET1, SER/PAR, CLK, DATA IN, UPDATE DATA OUT DATA OUT 2.0 V min 0.6 V max VDD − 0.3 V min DGND + 0.5 V max 1 μA max –1 μA min −1 mA max 1 mA min 1 See Figure 15. |
类似零件编号 - AD8118ABPZ |
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类似说明 - AD8118ABPZ |
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