MC33696FCE datasheet(11/64 Pages) FREESCALE

部件名	MC33696FCE

功能描述	PLL Tuned UHF Transceiver for Data Transfer Applications

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制造商	FREESCALE [Freescale Semiconductor, Inc]

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Register Access through SPI

MC33696 Data Sheet, Rev. 9

Freescale Semiconductor

11

The data transfer protocol for each mode is described in the following sections.

11.2 Configuration Mode

This mode is used to write or read the internal registers of the MC33696.

As long as a low level is applied to CONFB (see Figure 29), the MCU is the master node driving the SCLK

input, the MOSI line input, and the MISO line output. Whatever the direction, SPI transfers are 8-bit based

and always begin with a command byte, which is supplied by the MCU on MOSI. To be considered as a

command byte, this byte must come after a falling edge on CONFB. Figure 3 shows the content of the

command byte.

Bits N[1:0] specify the number of accessed registers, as defined in Table 6.

Bits A[4:0] specify the address of the first register to access. This address is then incremented internally

by N after each data byte transfer.

R/W specifies the type of operation:

0=Read

1=Write

Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when

reading).

Table 5. Serial Digital Interface Feature versus Selected Mode (SEB = 1)

Selected Mode

MC33696 Digital Interface Use

Configuration

SPI slave, data received on MOSI, SCLK from MCU, MISO is output

Transmit

SPI deselected, MOSI receives encoded data from MCU

Receive

DME = 1

SPI master, data sent on MOSI with clock on SCLK

DME = 0

SPI deselected, received data are directly sent to MOSI

Standby / LVD

SPI deselected, all I/O are high impedance

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

N1

N0

A4

A3

A2

A1

A0

R/W

Figure 3. Command Byte

Table 6. Number N of Accessed Registers

N[1:0]

Number N of Accessed Registers

00

1

01

2

10

4

11

8

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