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MC33696FCE 数据表(PDF) 7 Page - Freescale Semiconductor, Inc |
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MC33696FCE 数据表(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 64 page Supply Voltage Monitoring and Reset MC33696 Data Sheet, Rev. 9 Freescale Semiconductor 7 Figure 2. Wiring Diagrams A second voltage regulator supplies the digital part. This regulator is powered from pin VCCDIG and its output is connected to VCCDIG2. An external capacitor must be inserted between VCCDIG2 and GNDDIG, for decoupling. The supply voltage VCCDIG2 is equal to 1.6 V. In standby mode, this voltage regulator goes into an ultra-low-power mode, but VCCDIG2 = 0.7 x VCCDIG. This enables the internal registers to be supplied, allowing configuration data to be saved. 7 Supply Voltage Monitoring and Reset At power-on, an internal reset signal is generated. All registers are reset. When the LVDE bit is set, the low-voltage detection module is enabled. This block compares the supply voltage on VCCINOUT with a reference level of about 1.8 V. If the voltage on VCCINOUT drops below 1.8 V, status bit LVDS is set. The information in status bit LVDS is latched and reset after a read access. NOTE If LVDE = 1, the LVD module remains enabled. The circuit cannot be put in standby mode, but remains in LVD mode with a higher quiescent current, due to the monitoring circuitry. LVD function is not accurate in standby mode. 8 Receiver Functional Description The receiver is based on a superheterodyne architecture with an intermediate frequency (IF) of 1.5 MHz (see Figure 1). Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side 3V Operation 5V Operation 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 RSSIOUT VCC2RF RFIN GNDLNA VCC2VCO GNDPA1 RFOUT GNDPA2 SEB SCLK MOSI MISO CONFB DATACLK RSSIC GNDDIG VCC2 U11 MC33696 VCC2 3 V VCC2 VCC2 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 RSSIOUT VCC2RF RFIN GNDLNA VCC2VCO GNDPA1 RFOUT GNDPA2 SEB SCLK MOSI MISO CONFB DATACLK RSSIC GNDDIG VCC2 U11 MC33696 VCC2 5 V VCC2 VCC2 |
类似零件编号 - MC33696FCE |
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类似说明 - MC33696FCE |
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