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MC1321X 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

部件名 MC1321X
功能描述  ZigBee?? Compliant Platform - 2.4 GHz Low Power Transceiver for the IEEE짰 802.15.4 Standard plus Microcontroller
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MC1321X 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

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MC13211/212/213 Technical Data, Rev. 1.2
Freescale Semiconductor
21
4.6.2.2
SPI Transaction Operation
Although the SPI port of the MCU transfers data in bursts of 8 bits, the 802.15.4 modem requires that a
complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The
assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to
the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the 802.15.4
modem and a read is data written to the SPI master. The following SPI bursts will be either the write data
(MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the 802.15.4
modem never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can
extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high
to signal the end of the transaction.
An example SPI read transaction with a 2-byte payload is shown in Figure 11.
Figure 11. SPI Read Transaction Diagram
CE
SPICLK
MISO
MOSI
Valid
Valid
Valid
Clock Burst
Header
Read data


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