3D3424 datasheet(5/6 Pages) DATADELAY

部件名	3D3424

功能描述	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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制造商	DATADELAY [Data Delay Devices, Inc.]

网页	http://www.datadelay.com

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5 / 6 page

3D3424

Doc #06020

DATA DELAY DEVICES, INC.

5

6/6/2006

3 Mt. Prospect Ave. Clifton, NJ 07013

DEVICE SPECIFICATIONS

TABLE 3: ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

DC Supply Voltage

VDD

-0.3

7.0

V

Input Pin Voltage

VIN

-0.3

VDD+0.3

V

Input Pin Current

IIN

-10

10

mA

25C

Storage Temperature

TSTRG

-55

150

C

Lead Temperature

TLEAD

300

C

10 sec

TABLE 4: DC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Static Supply Current*

IDD

5.0

7.0

mA

VDD = 3.6V

High Level Input Voltage

VIH

2.0

V

Low Level Input Voltage

VIL

0.8

V

High Level Input Current

IIH

-0.1

0.0

0.1

µA

VIH = VDD

Low Level Input Current

IIL

-0.1

0.0

0.1

µA

VIL = 0V

High Level Output Current

IOH

-8.0

-6.0

mA

VDD = 3.0V

VOH = 2.4V

Low Level Output Current

IOL

6.0

7.5

mA

VDD = 3.0V

VOL = 0.4V

Output Rise & Fall Time

TR & TF

2

ns

CLD = 5 pf

*IDD(Dynamic) = 4 * CLD * VDD * F

Input Capacitance = 10 pf typical

where: CLD = Average capacitance load/line (pf)

Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

TABLE 5: AC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Latch Width

TLW

10

ns

Data Setup to Clock

tDSC

10

ns

Data Hold from Clock

tDHC

1

ns

Clock Width (High or Low)

tCW

15

ns

Clock Setup to Latch

tCSL

20

ns

Clock to Serial Output

tPCQ

12

20

ns

Latch to Delay Valid

tLDV

35

45

ns

1

Latch to Delay Invalid

tLDX

5

ns

1

Input Pulse Width

tWI

10

% of Total Delay

See Table 1

Input Period

Period

20

% of Total Delay

See Table 1

Input to Output Delay

tPLH, tPHL

ns

See Text

NOTES: 1 - Refer to PROGRAMMED DELAY UPDATE section

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