AD9898KCP-20 datasheet(5/52 Pages) AD

部件名	AD9898KCP-20

功能描述	CCD Signal Processor with Precision Timing??Generator

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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REV. 0

AD9898

–5–

TIMING SPECIFICATIONS (C

L = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz, unless otherwise noted.)

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK, CLI

CLI Clock Period

tCONV

50

ns

CLI High/Low Pulsewidth

20

25

ns

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

6ns

AFE CLAMP PULSES

*

CLPOB Pulsewidth

4

10

Pixels

AFE SAMPLE LOCATION

* (See Figure 13)

SHP Sample Edge to SHD Sample Edge

tS1

20

25

Pixels

DATA OUTPUTS (See Figure 15)

Output Delay from DCLK Rising Edge

tOD

9ns

Pipeline Delay from SHP/SHD Sampling

9

Cycles

SERIAL INTERFACE (See Figures 7 and 8)

Maximum SCK Frequency

fSCLK

10

MHz

SL to SCK Setup Time

tLS

10

ns

SCK to SL Hold Time

tLH

10

ns

SDATA Valid to SCK Rising Edge Setup

tDS

10

ns

SCK Falling Edge to SDATA Valid Hold

tDH

10

ns

SCK Falling Edge to SDATA Valid Read

tDV

10

ns

*Parameter is programmable.

Specifications subject to change without notice.

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AD9898KCP-20 数据表(PDF) 5 Page - Analog Devices

AD9898KCP-20 数据表(HTML) 5 Page - Analog Devices

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类似说明 - AD9898KCP-20

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