SN54LV161A, SN74LV161A

4BIT SYNCHRONOUS BINARY COUNTERS

SCLS404F − APRIL 1998 − REVISED DECEMBER 2005

8

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

TA = 25°C

SN54LV161A

SN74LV161A

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration

CLK high or low

7

7

7

ns

tw

Pulse duration

CLR low

7

7

7

ns

CLR

4.5

4.5

4.5

tsu

Setup time before CLK

↑

Data (A, B, C, and D)

7.5

8.5

8.5

ns

tsu

Setup time before CLK

↑

ENP, ENT

9.5

11

11

ns

LOAD low

10

11.5

11.5

th

Hold time, all synchronous inputs after CLK

↑

1.5

1.5

1.5

ns

(unless otherwise noted) (see Figure 1)

TA = 25°C

SN54LV161A

SN74LV161A

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration

CLK high or low

5

5

5

ns

tw

Pulse duration

CLR low

5

5

5

ns

CLR

2.5

2.5

2.5

tsu

Setup time before CLK

↑

Data (A, B, C, and D)

5.5

6.5

6.5

ns

tsu

Setup time before CLK

↑

ENP, ENT

7.5

9

9

ns

LOAD low

8

9.5

9.5

th

Hold time, all synchronous inputs after CLK

↑

1

1

1

ns

(unless otherwise noted) (see Figure 1)

TA = 25°C

SN54LV161A

SN74LV161A

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration

CLK high or low

5

5

5

ns

tw

Pulse duration

CLR low

5

5

5

ns

CLR

1.5

1.5

1.5

tsu

Setup time before CLK

↑

Data (A, B, C, and D)

4.5

4.5

4.5

ns

tsu

Setup time before CLK

↑

ENP, ENT

5

6

6

ns

LOAD low

5

6

6

th

Hold time, all synchronous inputs after CLK

↑

1

1

1

ns

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design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.