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VDG−03174

7 Current-Limit Trips

(HDRV Cycle Terminated by Current-Limit Trip)

7

Soft-Start

Cycles

HDRV

Clock

SS

LOOP COMPENSATION

SHUTDOWN AND SEQUENCING

TPS40077

SLUS714 – JANUARY 2007

APPLICATION INFORMATION (continued)

Figure 25. Typical Fault Protection Waveforms

Voltage-mode, buck-type converters are typically compensated using Type III networks. Because the TPS40077

uses voltage feed-forward control, the gain of the voltage feed-forward circuit must be included in the PWM gain.

The gain of the voltage feed-forward circuit, combined with the PWM circuit and power stage for the TPS40077

is:

The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage

feed-forward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a

function of the programmed startup voltage.

The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers

are in the low-output state, turning off both of the power FETs. This places the output of the converter in a

high-impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slow

pulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As a

general rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of

the control loop crossover frequency. An example of a shutdown interface is shown in Figure 26.

19

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